The present invention relates generally to integrated circuits and more particularly to complimentary metal oxide semiconductor (CMOS) integrated circuits. The present invention more particularly relates to clock generators for clocking CMO integrated circuit microprocessors which provide a clock signal having first and second phases of sufficient duration to accommodate internal microprocessor delays resulting from microprocessor speed paths.
CMOS integrated circuit microprocessors, for proper operation thereof, generally must be clocked by a clock signal having a first phase and a second phase for each clock cycle period. The clock signal first phase is at a high level for a first execution time period and the second phase is at a low level for a second execution time period to complete each clock cycle. The reason for this clocking procedure is that CMOS integrated circuits include circuitry wherein a first portion of the circuitry is active during the high level first phase of the clock signal and the other or second portion of the circuitry is active during the low level second phase of the clock signal.
The first and second phases of each clock signal cycle must be of sufficient duration to enable both portions of the microprocessor circuitry to complete their execution. Each such portion requires some finite minimum execution time because of internal microprocessor delays resulting from internal speed paths. The speed paths for each portion need not be, and generally are not, uniform. Hence, the first circuitry portion may have speed paths which are longer than the speed paths of the second circuitry portion, requiring the first clock signal phase to be longer than the second clock signal phase.
In addition to the foregoing, the internal speed paths and resulting first and second minimum execution time periods are greatly affected by integrated circuit processing parameters, microprocessor operating temperature, and microprocessor operating supply voltage. For example, microprocessors execute more slowly as operating temperature increases. Microprocessors also execute more slowly as the operating supply voltage decreases. In either or both of these cases, the duration of the first and second clock signal phases must be extended to provide first and second execution times which are sufficient to accommodate the increased first and second minimum execution time periods.
From the foregoing, it can be appreciated that if the first and second clock corresponding first and second minimum execution time periods, the microprocessor being clocked will not function properly because it will not have sufficient time during one or both of the first or second phases to complete its executions. This condition can occur if the clock signal frequency is too high or if the duty cycle of the clock signal represented by the duration of the first and second phases is expressively skewed resulting in one of the phases being shorter in duration than its corresponding minimum execution time period.
Clock generators for providing such clock signals are generally provided "on chip" in CMOS microprocessor devices. However, they develop the clock signal or signals in response to input clock signals generated by external clock sources. The on chip clock generators must be arranged to provide the clock signal first and second phase durations because the external clock sources cannot always be relied upon to provide such clock signals. In fact, the external clock sources usually provide input clock signals at a frequency and duty cycle in a wide range and which do not allow for changes in microprocessor operating speed. It is therefore required that the on chip clock generators be able to derive the clock signals for clocking the microprocessor responsive to input clock signals having a wide range of frequencies and duty cycles.
One common on chip circuit arrangement for providing appropriate clock signals has included phase-locked loops. Phase-locked loops, while being generally successful in this regard, do suffer from a number of disadvantages. Such circuits are expensive to implement because they require a high number of components and thus occupy a considerable portion of the integrated circuit die area. Also, phase-locked loops do not accommodate as wide a range of input clock signal duty cycles and frequencies which might be desired. Furthermore, phase-locked loops require some degree of start-up time to generate the proper clock signals after power is initially applied to the microprocessors utilizing such circuitry.
Another method is to employ internal circuitry for dividing down an externally applied 2X clock signal to derive a 1X clock having the desired duty cycle. The problem with this technique however is that 2X clocks are much more expensive and difficult to implement, especially as clock frequencies increase.
Hence, there is a need in the art for an improved self-regulating clock generator which may be incorporated in chip in CMOS devices such as microprocessors. Preferably, the improved clock generator should incorporate fewer components than phase-locked loops resulting in less die area and hence less implementation cost. Further, the improved clock generator should be able to generate suitable first and second clock signal phases without the need of a 2X clock and from the time in which power is initially applied to such devices without a start-up time. The improved clock generator should also be more tolerant to instantaneous external input clock signal frequency and duty cycle variations, and variations in microprocessor operating speed as a result of changes in temperature or supply voltages, for example.